>If a vendor doesn't work out, just move to another RISC-V vendor.
It doesn't really work that way. NASA needs two main things that most vendors can't supply: a radiation-hardened chip, and super-high quality controls. Implementing on an FPGA is much slower than an ASIC, but the ESA did it with the LEON3 processor.
Radiation hardening can come in a variety of ways, from redundant designs (3-core voting, EDAC) to manufacturing processes (silicon-on-insulator, gate structures) to even packaging (high density ceramic). These have very little overlap with commercial applications, so the vendor choice is still very limited.
It seems like it also wouldn't be enough to just declare the fpga itself hardened. It might need to certified for a specific setup, as even small design changes could cause significant moving around of logic that could change the ability to recover from a SEU.
I dunno, it's a bit fuzzy, I don't recall general layout issues when it came to rad stuff.
If you are in an environment where you are that worried about an upset, you're likely using a rad tolerant fpga.
Parent comment mentions 3-core voting which is a good callout. Ime a lot (most?) rad hard fpgas have a sort of voting logic baked into the flip-flops, its sort of transparent to the synthesizer. They usually have an upset immunity to a certain energy particle.
Transients are a different story, and RAM or clock resources you can find require some consideration.
It doesn't really work that way. NASA needs two main things that most vendors can't supply: a radiation-hardened chip, and super-high quality controls. Implementing on an FPGA is much slower than an ASIC, but the ESA did it with the LEON3 processor.
Radiation hardening can come in a variety of ways, from redundant designs (3-core voting, EDAC) to manufacturing processes (silicon-on-insulator, gate structures) to even packaging (high density ceramic). These have very little overlap with commercial applications, so the vendor choice is still very limited.