It seems like it also wouldn't be enough to just declare the fpga itself hardened. It might need to certified for a specific setup, as even small design changes could cause significant moving around of logic that could change the ability to recover from a SEU.
I dunno, it's a bit fuzzy, I don't recall general layout issues when it came to rad stuff.
If you are in an environment where you are that worried about an upset, you're likely using a rad tolerant fpga.
Parent comment mentions 3-core voting which is a good callout. Ime a lot (most?) rad hard fpgas have a sort of voting logic baked into the flip-flops, its sort of transparent to the synthesizer. They usually have an upset immunity to a certain energy particle.
Transients are a different story, and RAM or clock resources you can find require some consideration.
